• The receiving side of the AM-RLC entity receives AMD and Control PDUs through the configured logical channels from the lower layer.
• AMD PDUs are routed to the Deciphering Unit and then delivered to the Reception buffer.
• The AMD PDUs are placed in the Reception buffer until a complete RLC SDU has been received. The Receiver acknowledges successful reception or requests retransmission of the missing AMD PDUs by sending one or more STATUS PDUs to the AM RLC peer entity, through its transmitting side.
• The associated AMD PDUs are reassembled by the Reassembly Unit and delivered to upper layers through the AM-SAP.
• RESET and RESET ACK PDUs are delivered to the RLC Control Unit for processing. If a response to the peer AM RLC entity is needed, an appropriate Control PDU is delivered, by the RLC Control Unit to the transmitting side of the AM RLC entity.
• The transmitting side of the AM-RLC entity receives RLC SDUs from upper layers through the AM-SAP.
• RLC SDUs are segmented and/or concatenated into AMD PDUs of a fixed length.
– The segmentation is performed if the received RLC SDU is larger than the length of available space in the AMD PDU.
– The PDU size is set during AM-RLC establishment.
– The packets could be segmented, concatenated, padded.
– Boundaries between the packets are indicated by a length indicator.
• After the segmentation and/or concatenation are performed, the AMD PDUs are placed in the Retransmission buffer at the MUX.
• AMD PDUs buffered in the Retransmission buffer are deleted or retransmitted.
• The MUX multiplexes AMD PDUs from the Retransmission buffer that need to be retransmitted, and the newly generated AMD PDUs delivered from the Segmentation/Concatenation function.
• The PDUs are delivered to the function that completes the AMD PDU header and potentially replaces padding with piggybacked status information. A Piggybacked STATUS PDUs can be of variable size in order to match the amount of free space in the AMD PDU.
• The ciphering (if configured) is then applied to the AMD PDUs.
– The AMD PDU header is not ciphered.
– Control PDUs (i.e. STATUS PDU, RESET PDU, and RESET ACK PDU) are not ciphered.
• AMD PDUs are submitted to either one or two DCCH or DTCH logical channels.
